Phil James Roxby, AMD
New compute architectures with high performance cores, distributed memories and hardware accelerated data movement are becoming available in new form factors, even finding their ways into laptops. In this talk, I will discuss one such architecture, AMD’s AI Engine, and show how researchers are taking advantage of open source code to map their applications onto this spatial architecture.
During the talk, I will highlight the unique features of the AI Engine, and describe how open source is making these devices more accessible including new capabilities like dynamic dispatch of kernels. In addition, I will describe an application ported to the AI Engines which is able to outperform CPUs and GPUs to show the breadth of target applications possible on these spatial compute devices.
Phil has a PhD from the University of Manchester on implementing ML applications on programmable logic, and worked at the University of Birmingham as a lecturer, where his research interests included cryptography on programmable logic as well as general new design tools for IP reuse. He joined Xilinx in 2000, and has been responsible for a number of programs including the AI Engine, SDAccel and SDNet. Most recently, Phil is working on tools to make AI Engines more widely accessible now as part of AMD.
"Chameleon: a Disaggregated CPU, GPU, and FPGA System for Retrieval-Augmented Language Models"
Wenqi Jiang and Gustavo Alonso
"Enabling Communication with FPGA-Based Network-Attached Accelerators for HPC Workloads"
"Tydi-lang: A Language for Typed Streaming Hardware"
Yongding Tian, Matthijs Reukers, Zaid Al-Ars, Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, and Jeroen Straten
"Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs"
Christoph Weckert, Leonardo Solis-Vasquez, Julian Oppermann, Andreas Koch, and Oliver Sinnen
"OctoRay: Framework for Scalable FPGA Cluster Acceleration of Python Big Data Applications"
Zaid Al-Ars, Jakoba Petri-Koenig, Joost Hoozemans, Luc Dierick, and H. Peter Hofstee
"Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA"
Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Emilien Bauer, Anton Lydike, and Tobias Grosser