Agenda

"Programming Methods, Architectures, and Applications of Reconfigurable Technologies in HPC" [slides]
Andreas Koch, TU Darmstadt

"Enabling VirtIO Driver Support on FPGAs" [slides]
Martin Herbordt, Boston University

Break

"A First Step towards Support for MPI Partitioned Communication on SYCL-programmed FPGAs" [slides]
Steffen Christgau, Zuse Institute Berlin

"Fast and energy-efficient derivatives risk analysis: Streaming option Greeks on Xilinx and Intel FPGAs"
Mark Klaisoongnoen, Edinburgh Parallel Computing Centre (EPCC)

"Accelerating Kernel Ridge Regression with Conjugate Gradient Method for large-scale data using FPGA High-level Synthesis"
Yousef Alnaser, Fraunhofer Institute for Electronic Nano Systems

Lunch

"PYNQ for HPC" [slides]
Graham Schelle, AMD/Xilinx

Abstract: PYNQ is an open-source project from AMD that aims to help HPC applications achieve performance goals quicker by lowering software complexity. PYNQ with its runtime Python APIs has its roots in Zynq SoCs (ARM processors plus programmable logic) and has expanded across both datacenter and RFSoC adaptive computing platforms. With that expansion, the PYNQ community now numbers in 1000’s of active users across 10’s of thousands shipped platforms. In this short talk, PYNQ will be revisited in the context of cloud and quantum computing – both areas where adaptive computing is appearing in larger HPC frameworks. PYNQ has provided a scalable API for cloud deployments for some time and more recently has been deployed within new quantum computing control systems. Lastly, our newest project, PYNQ-Metadata, will be introduced - this work gives users new levels of hardware introspection into existing (and new) hardware designs, all from within Jupyter notebooks.

Bio: Graham Schelle is a fellow at AMD within the Adaptive and Embedded Computing Group (AECG). He is the lead maintainer of both the PYNQ and the RFSoC-PYNQ open-source projects. He has also led various research efforts on SoC performance analysis and productivity language support while at AMD and formerly Xilinx. Graham is also a member of AECG’s Office of Open Source.

"MLIR Compilers for Heterogeneous Computing" [slides]
Stephen Neuendorffer, AMD/Xilinx Research Labs

Abstract: With the slowing of CMOS technology scaling trends and the continued growth of compute requirements for applications like 5G wireless and machine learning, there has been a widespread emphasis on new accelerator architectures emphasizing heterogeneity. However, programming heterogeneous devices can be challenging, requiring heterogenous design tools supporting multiple levels of abstraction. This talk will discuss how MLIR, a new compiler infrastructure which directly supports multiple levels of abstraction, can enable these new design tools to support next generation heterogeneous systems.

Bio: Stephen Neuendorffer is a Fellow at AMD in the Adaptive and Embedded Computing Group working on early development of compilation for compute acceleration, focused on leveraging LLVM and MLIR. Previously, he was product architect of Xilinx Vivado HLS, co-authored a widely used textbook on HLS design for FPGAs, and worked with customers on a wide variety of applications, including video encoders, computer vision, wireless systems, and networking systems. He received B.S. degrees in Electrical Engineering and Computer Science from the University of Maryland, College Park in 1998. He graduated with University Honors, Departmental Honors in Electrical Engineering, and was named the Outstanding Graduate in the Department of Computer Science. He received the Ph.D. degree from the University of California, Berkeley in 2005, after being one of the key architects of Ptolemy II.

"Virtual Screening on FPGA: Performance and Energy versus Effort" [slides]
Tom Vander Aa, Interuniversity Microelectronics Centre (IMEC), Belgium

Open Slot

Break

"Stencils, Solvers, and Sphere Decoders on FPGAs" [slides]
Suhaib Fahmy, King Abdullah University of Science and Technology (KAUST)

"SYCL and RISC-V"
Michael Wong, Codeplay

Abstract: In this talk we will demonstrate our RISC-V accelerated computing stack with SYCL and oneAPI for HPC and AI. We will also demo it on an FPGA and demonstrate to attendees how they can get it working themselves and also how they can customize their own hardware design while still running HPC applications.

"Overview of the HACC Program" [slides]
Christian Plessl, Paderborn University

Closing Remarks