Agenda
9:00 am
Opening Remarks
9:05 am
"Hardware Specialization for Efficiency and Performance"
Derek Chiou, Microsoft Research
10:00 pm
Break
10:30 am
"ACCL: FPGA-Accelerated Collectives over 100 Gbps TCP-IP"
Zhenhao He, Xilinx Research Dublin
11:00 am
"Near-Data FPGA-Accelerated Processing of Collective and Inference Operations in Disaggregated Memory Systems"
Carsten Heinz, TU Darmstadt
11:30 am
"Efficient HW and SW Interface Design for Convolutional Neural Networks Using High-Level Synthesis and TensorFlow"
Ashish Mishra, NCSA
12:00 am
"Optimizing a Hardware Network Stack to Realize an In-Network ML Inference Application"
Marco Hartmann, Technical University of Darmstadt
12:30 am
Lunch
2:00 pm
"Optimized Implementation of the HPCG Benchmark on Reconfigurable Hardware"
Alberto Zeni, Politecnico Di Milano
2:30 pm
"A Framework for Customizable FPGA-based Image Registration Accelerators"
Davide Conficconi, Politecnico Di Milano
3:00 pm
Break
3:30 pm
"The Open Cloud Testbed: A Resource for FPGA and Cloud Researchers"
Miriam Leeser, Northeastern University
3:45 pm
"Enhancing the Scalability of the Multi-FPGA Stencil Computations via Highly Optimized HDL Components"
Emanuele Del Sozzo, Politecnico Di Milano
4:15 pm
"Device_global: A SYCL Extension Introducing Device-Scoped Allocations to Enhance Performance and Usability"
Michael Kinsner, Intel
4:30 pm
"Portable Compilation of NumPy to FPGAs"
Johannes de Fine Licht, ETH Zurich
4:45 am
"Porting in-compressible flow matrix assembly to FPGAs for accelerating HPC engineering simulations"
Nick Brown, University of Edinburgh