Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'16)

Held in conjunction with SC16
Monday, November 14, 2016 ** updated date! **
Salt Lake City, UT

Link to last year's (2015) workshop here.

With Exascale systems on the horizon at the same time that conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy-efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads of general-purpose architectures–for example, through customized datapaths and memory architectures–and can thus achieve much higher energy efficiencies compared to conventional CPU- and GPU-based solutions. This has stimulated interest in their exploitation within power-hungry data centers, with recent benchmarks showing that FPGA-based application acceleration can achieve up to 25X better performance per watt and 50-75x performance improvement compared to CPU/GPU implementations.

Although the potential for FPGAs within HPC continues to be demonstrated by various research on FPGA acceleration, most of this work has directly implemented the functions of interest through cumbersome, hardware-centric RTL flows—the traditional FPGA development path. However, to maximize productivity and adoption, the HPC community will benefit from a more conventional programming model. With this challenge in mind, leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier to use, design entries for programming FPGAs, including the OpenCL framework, already widely used by the HPC community for heterogeneous computing. OpenCL is particularly appealing because it offers the potential for portability to GPUs and Xeon Phi.

Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures in terms of both performance and energy consumption, with increasing relevance to the challenges faced on the road to Exascale. With this in mind, this will be a unique workshop at SC that brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on how newly-available high-level programming models, including OpenCL, are already empowering HPC software developers to directly leverage FPGAs, and to identify future opportunities and needs for research in this area.

Call for Papers

***Submission Link***

Workshop Organizers:
Michaela Blott, Xilinx
Michael Lysaght, ICHEC
Torsten Hoefler, ETH Zurich
Jason D. Bakos, University of South Carolina